Delay-Compensation Flip-Flops for Timing-Error Tolerant Circuit Design

1. Introduction As the clock frequency and circuit integrity have been increased exponentially, power consumption has also increased drastically and process variations have been becoming a big issue. One of the most effective methods for low power computation is dynamic voltage scaling (DVS) with in-situ timing-error detection. Furthermore, it is robust to parameter variations in the extremely scaled technology generations and can minimize timing and voltage margins, because supply voltage is dynamically tuned during circuit operation, or after every fabrication process is finished. However, conventional methods for in-situ timing-error monitoring have some disadvantages: the decrease of the degree of freedom for designing circuits and the necessity of the complex recovery mechanism for timing errors. The delay-compensation flip-flop (DCFF) automatically regulates its control signal as it finds the boundary between two successive data with error detection. The purpose of this paper is to present how DCFF can substantially improve the problems mentioned above, compared to conventional methods described in the section 2.